A 65nm CMOS Ramp Generator Design and its Application Towards a BIST Implementation of the Reduced-Code Static Linearity Test Technique for Pipeline ADCs

作者：Renaud Guillaume^*; Barragan Manuel J; Laraba Asma; Stratigopoulos Haralampos G; Mir Salvador; Le Gall Herve; Naudet Herve

来源：Journal of Electronic Testing-Theory and Applications, 2016, 32(4): 407-421.

DOI：10.1007/s10836-016-5599-8

• Analog-to-Digital converters
• On-chip ramp generator
• Built-In Self-Test
• Static linearity testing
• Reduced-code linearity testing

This work presents an efficient on-chip ramp generator targeting to facilitate the deployment of Built-In Self-Test (BIST) techniques for ADC static linearity characterization. The proposed ramp generator is based on a fully-differential switched-capacitor integrator that is conveniently modified to produce a very small integration gain, such that the ramp step size is a small fraction of the LSB of the target ADC. The proposed ramp generator is employed in a servo-loop configuration to implement a BIST version of the reduced-code linearity test technique for pipeline ADCs, which drastically reduces the volume of test data and, thereby, the test time, as compared to the standard test based on a histogram. The demonstration of the pipeline ADC BIST is carried out based on a mixture of transistor-level and behavioral-level simulations that employ actual production test data.

• 出版日期2016-8