An Opampless Second-Order MASH Delta Sigma ADC with Using Gated Ring Oscillator Time-to-Digital Converter

作者：Konishi Toshihiro^*; Okuno Keisuke; Izumi Shintaro; Yoshimoto Masahiko; Kawaguchi Hiroshi

来源：IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences, 2013, E96A(2): 434-442.

DOI：10.1587/transfun.E96.A.434

• ADC
• TDC
• oscillator
• noise-shaping
• low-power
• small area
• process scalable

This paper presents a second-order Delta Sigma analog-to-digital converter (ADC) operating in a time domain. In the proposed ADC architecture, a voltage-controlled delay unit (VCDU) converts an input analog voltage to a delay time. Then, the clocks outputs from a gated ring oscillator (GRO) are counted during the delay time. No switched capacitor or opamp is used. Therefore, the proposed ADC can be implemented in a small area and with low power. For that reason, it has process scalability: it can keep pace with Moore%26apos;s law. A time error is propagated to the second GRO by a multi-stage noise-shaping (MASH) topology, which provides second-order noise-shaping. In a standard 40-nm CMOS process, a SNDR of 45 dB is achievable at input bandwidth of 16 kHz and a sampling rate of 8 MHz, where the power is 408.5 mu W. Its area is 608 mu m(2).

• 出版日期2013-2