An 11 b 7 ps Resolution Two-Step Time-to-Digital Converter With 3-D Vernier Space

作者：Kim Yeomyung^*; Kim Tae Wook

来源：IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2014, 61(8): 2326-2336.

DOI：10.1109/TCSI.2014.2304656

• High integrated nonlinearity
• redundancy and error correction
• time-of-flight (ToF) application
• time-to-digital converter (TDC)
• zoom-in architecture
• 3-D Vernier space

This paper presents a fine-resolution time-to-digital converter (TDC) with a large dynamic range using a 3-D Vernier space. Despite the wide dynamic range, the required delay cells in the delay-lines are minimized, leading to better power efficiency. The proposed TDC also exploits the redundancy and error-correction technique to solve the offset error of coarse conversion in the 3-D Vernier space architecture. The TDC is implemented using a 0.13-mu m CMOS process. The measurement result shows a dynamic range with an 11-bit 6.98-ps resolution, an integrated nonlinearity of +/- 1.5 LSB, a power consumption of 328.8 mu W, and a die area of 0.28 mm(2).

• 出版日期2014-8