A Dual-Clock VLSI Design of H.265 Sample Adaptive Offset Estimation for 8k Ultra- HD TV Encoding

作者：Zhou Jianbin; Zhou Dajiang; Wang Shihao; Zhang Shuping; Yoshimura Takeshi; Goto Satoshi

来源：IEEE Transactions on Very Large Scale Integration Systems, 2017, 25(2): 714-724.

DOI：10.1109/TVLSI.2016.2593581

• Dual-clock architecture
• H. 265
• high efficiency video coding (HEVC)
• sample adaptive offset (SAO)
• video coding
• VLSI

Sample adaptive offset (SAO) is a newly introduced in-loop filtering component in H. 265/High Efficiency Video Coding (HEVC). While SAO contributes to a notable coding efficiency improvement, the estimation of SAO parameters dominates the complexity of in-loop filtering in HEVC encoding. This paper presents an efficient VLSI design for SAO estimation. Our design features a dual-clock architecture that processes statistics collection (SC) and parameter decision (PD), the two main functional blocks of SAO estimation, at high-and lowspeed clocks, respectively. Such a strategy reduces the overall area by 56% by addressing the heterogeneous data flows of SC and PD. To further improve the area and power efficiency, algorithm-architecture co-optimizations are applied, including a coarse range selection (CRS) and an accumulator bit width reduction (ABR). CRS shrinks the range of fine processed bands for the band offset estimation. ABR further reduces the area by narrowing the accumulators of SC. They together achieve another 25% area reduction. The proposed VLSI design is capable of processing 8k at 120-frames/s encoding. It occupies 51k logic gates, only one-third of the circuit area of the state-of-the-art implementations.

• 出版日期2017-2