科研之友
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摘要
An output-capacitorless low-dropout regulator (LDO) based on an evolved versions of flipped voltage follower (FVF) has been proposed and simulated in a commercial 0.18 mu m CMOS process in this paper. To get over the tradeoff between power consumption against other important design parameters such as loop stability and fast response, the proposed LDO is based on FVF with a push-pull stage and adopts adaptive power transistors technique, which transforms the regulator between two-stage and three-stage amplifier for different load currents. Based on such topology, more measurements are utilized to further reduce transient overshoot and improve load regulation. Simulation results verify that the recovery time is as short as 1.3 mu s and the maximum undershoot and overshoot are as low as 39 mV and 42 mV, respectively. In addition, due to the adaptive power transistors technique, the quiescent current is only 16.6 mu A when the load current is light. Besides, excellent load regulation is obtained as 2.7 mu V/mA.
