A 5 Gb/s Energy-Efficient Voltage-Mode Transmitter Using Time-Based De-Emphasis

作者：Saxena Saurabh^*; Nandwana Romesh Kumar; Hanumolu Pavan Kumar

来源：IEEE Journal of Solid-State Circuits, 2014, 49(8): 1827-1836.

DOI：10.1109/JSSC.2014.2317142

• Digital phase-locked loop (DPLL)
• PWM equalization
• voltage-mode TX
• wireline

In this paper, we present a time-based equalization scheme to implement transmit de-emphasis in voltage-mode drivers. Using two-level pulse-width modulation, this work decouples the tradeoff between impedance matching, output swing, and de-emphasis resolution in conventional voltage-mode drivers using voltage-based de-emphasis. A prototype PWM-based 5 Gb/s voltage-mode transmitter was implemented in a 90 nm CMOS process and characterized across different channels and output swings. The horizontal/vertical eye opening (BER = 10(-12)) at the end of 60 and 96 in stripline channels is 78 mv/0.6 UI and 8 mV/0.3 UI, respectively. Duty cycle distortion of the clock severely reduced the margins, so the overall performance can be improved by applying duty-cycle correction to clock signals. The transmitter consumes a total power 15.6 mW of which 2.5 mW is consumed in the digital PLL and 7.8 mW in the pre-/output drivers and regulators. This translates to a power efficiency of 3.1 mW/Gb/s, which compares favorably with the state of the art.

• 出版日期2014-8