Fast architecture for decimal digit multiplication

作者：Fazlali Mahmood^*; Valikhani Hadi; Timarchi Somayeh; Malazi Hadi Tabatabaee

来源：Microprocessors and Microsystems, 2015, 39(4-5): 296-301.

DOI：10.1016/j.micpro.2015.01.004

• Computer arithmetic
• Binary coded decimal (BCD) encoding
• Binary and BCD multiplication
• Binary to BCD conversion

BCD digit multiplication module (BDM) is widely used in BCD arithmetic, especially in Decimal Floating-Point (DFP) units. In this paper, we present a new BCD digit multiplication scheme to accelerate this module. Similar to previous articles, our multiplier includes two parts contained binary multiplier and binary to BCD converter. Our contribution towards these modules can successfully overcome the previous BCD digit multipliers. The results indicate 19% hardware acceleration for the proposed multiplier architecture which is comparable to the best previous techniques in UMC 65 nm CMOS standard cells library hardware implementation. Therefore, the proposed BCD digit multiplier is an appropriate candidate to be utilized in BCD arithmetic units.

• 出版日期2015-7