A Cyclic Vernier TDC for ADPLLs Synthesized From a Standard Cell Library

作者：Park Youngmin^*; Wentzloff David D

来源：IEEE Transactions on Circuits and Systems I-Regular Papers, 2011, 58(7): 1511-1517.

DOI：10.1109/TCSI.2011.2158490

• All-digital PLL (ADPLL)
• standard cell library
• synthesis
• time-to-digital converter (TDC)
• Vernier

This paper presents a cyclic Vernier time-to-digital converter (TDC) with digitally controlled oscillators (DCOs), targeted for a synthesizable all-digital phase locked loop (ADPLL). All functional blocks in the TDC are implemented with digital standard cells and placed-and-routed (P&R) by automatic design tools; thus, the TDC is portable and scalable to other process technologies. The effect of P&R mismatch is characterized in calibration mode, and utilized to achieve a minimum TDC resolution of 5.5 ps. The TDC was fabricated in a 65 nm CMOS process, and occupies 0.006 mm(2).

• 出版日期2011-7