A 40-nm 256-Kb Half-Select Resilient 8T SRAM with Sequential Writing Technique

作者：Yoshimoto S^*; Terada M; Okumura S; Suzuki T; Miyano S; Kawaguchi H; Yoshimoto M

来源：IEICE Electronics Express, 2012, 9(12): 1023-1029.

DOI：10.1587/elex.9.1023

• SRAM
• 8T
• disturb
• half-select

This paper introduces a novel half-select resilient dual write wordline 8T (DW8T) SRAM with a sequential writing technique. The dual write wordlines are sequentially activated in a write cycle, and its combination with the half-VDD precharge suppresses the half-select problem. We implemented a 256-Kb DW8T SRAM and a half-VDD generator with a 40-nm CMOS process. The measurement results of the seven samples show that the proposed DW8T SRAM achieves a VDDmin of 600mV and improves the average VDDmin by 367mV compared to the conventional 8T SRAM. The measured leakage power can be reduced by 25%.

• 出版日期2012