An 8-bit 19 MS/s low-power 0.35 mu m CMOS pipelined ADC for DVB-H

作者：Palomo B^*; Munoz F; Carvajal R G; Garcia J R; Marquez F

来源：Integration, the VLSI Journal, 2012, 45(2): 222-227.

DOI：10.1016/j.vlsi.2011.10.003

• Pipelined ADC
• CMOS analog integrated circuits
• Low power
• Low voltage
• Opamp-sharing

This paper proposes an 8b 19 MHz CMOS pipelined analog-to-digital converter (ADC) for DVB-H. In order to reduce the power consumption a combination of techniques has been used, such as op-amp sharing, low-power amplifiers with gain boosting and an aggressive capacitor scaling. The prototype ADC fabricated in 0.35 mu m CMOS demonstrates a maximum differential nonlinearity (DNL) of 0.63 least significant bit (LSB) and a maximum integral nonlinearity (INL) of 0.58 LSB with a peak signal-to-noise-and-distortion ratio (SNDR) and spurious-free dynamic range (SFDR) of 42.76 and 51.57 dB at 19 MHz. The ADC with an active area of 4.78 mm(2) consumes less than 4 mW at the mentioned sampling frequency.

• 出版日期2012-3