Application-Independent Testing of 3-D Field Programmable Gate Array Interconnect Faults

作者：Peng Yen Lin^*; Kwai Ding Ming; Chou Yung Fa; Wu Cheng Wen

来源：IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2014, 22(2): 207-219.

DOI：10.1109/TVLSI.2013.2242100

• Delay fault
• field-programmable gate array (FPGA) testing
• interconnect test
• open fault (OF)
• short fault (SF)
• 3-D FPGA
• universal test

3-D integration has been touted as an approach to reducing the lengths of critical paths in field-programmable gate arrays (FPGAs). A 3-D chip stacks a number of 2-D FPGA bare dies, interconnected by through-silicon vias (TSVs) and micro bumps, to attain a high packing density. However, the technology also introduces new types of defects, such as TSV void and microbump misalignment. Testing the interconnection faults becomes inevitable. In this paper, we present an automatic test pattern generator for open, short, and delay faults on 3-D FPGA interconnects by exploiting the regularity of switch matrix topology and forming repetitive paths with finite steps and with loop-back. The experimental results show that 12 test patterns (TPs) suffice to achieve 100% open fault coverage (FC). To detect all possible neighboring short faults, we need more than 40 TPs, whose number increases only slightly with the height of the 3-D FPGA. The TPs have high delay FC (96%) for 3-D FPGAs with the number of configurable logic blocks ranging from 50 x 50 x 2 to 50 x 50 x 6, demonstrating the scalability of our method.

• 出版日期2014-2
• 单位清华大学