科研之友
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摘要
In this article, we present a new iterative algorithm aimed at improving the performance of the sigma-delta analog to digital (A/D) converter. We subject the existing sigma-delta modulator, without changing the configuration, to an iterative procedure to increase the signal-to-noise ratio of the reconstructed signal. In other words, we demonstrate that sigma-delta modulated signals can be decoded using the iterative algorithm. Simulation results confirm that the proposed method works very well, even when less complex filters are used. The simple and regular structure of this new A/D converter, not only makes realization of the hardware as ASIC or on FPGA boards easy, but also allows it to operate at high frequency levels with optimized power consumption and small chip area. Implementation of the design with an FPGA shows that experimental results are in agreement with the simulation results.
- 出版日期2012
