A Fully-Integrated 40-Gb/s Transceiver in 65-nm CMOS Technology

作者：Chen Ming Shuan^*; Shih Yu Nan; Lin Chen Lun; Hung Hao Wei; Lee Jri

来源：IEEE Journal of Solid-State Circuits, 2012, 47(3): 627-640.

DOI：10.1109/JSSC.2011.2176635

• Clock and data recovery (CDR)
• equalizer
• finite-inpulse response (FIR) filter
• majority voting
• transceiver (TRx)

This paper introduces a fully-integrated wireline transceiver operating at 40 Gb/s. The transmitter incorporates a 5-tap finite-inpulse response (FIR) filter with LC-based delay lines precisely adjusted by a closed-loop delay controller. The receiver employs a similar 3-tap FIR filter as an equalizer front-end with digital adaptation, and a sub-rate clock and data recovery circuit using majority voting phase detection. The transceiver delivers 40-Gb/s 2(7) - 1 PRBS data across a Rogers channel of 20 cm (19-dB loss at 20 GHz) with BER < 10(-12) while consuming a total power of 655 mW.

• 出版日期2012-3
• 单位中国科学院电工研究所