摘要

This paper presents an integrated circuit (IC) implementation of a hybrid switched capacitor converter based on a modified series-parallel architecture. The converter operates in a quasi-resonant mode to regulate a nominal 3.7 V output from a 12 V supply. The design uses zero-current detection and nested 1-b regulation to autotune the zero-current switching state, simplify the design of a digital voltage-mode control scheme, and achieve partial zero-voltage switching. The modified architecture is able to operate with single-voltage rated devices without degrading the voltage times current product of the converter. This paper discusses details of level shifting, gate driving, and bootstrapping for an all n-channel powertrain, including a precharge circuit, to facilitate safe startup. The converter IC was designed in 180-nm bulk CMOS with a 5 V option for power devices. It was tested in a flip-chip assembly with a 36 nH 0402 inductor to deliver up to 4.6 W at 87.5% efficiency at a power density of 0.23 W/mm(3).

  • 出版日期2018-6