A counter-based all-digital spread-spectrum clock generator with high EMI reduction in 65 nm CMOS

作者：Chung Ching Che^*; Sheng Duo; Ho Wei Da

来源：IEICE Electronics Express, 2013, 10(6): 20130090.

DOI：10.1587/elex.10.20130090

• EMI reduction
• ADPLL
• SSCG

An all-digital spread-spectrum clock generator (ADSSCG) with direct modulation on the digitally controlled oscillator (DCO) is presented. The proposed ADSSCG can generate an accurate triangular modulation on the output frequency, and thus it can achieve high electromagnetic interference (EMI) reduction with a smaller spreading ratio as compared with existing designs. In addition, the proposed frequency counter-based mechanism can maintain the long-term frequency stability of the ADSSCG. The proposed ADSSCG is implemented in a standard performance 65 nm CMOS process, the active area is 85 mu m x 85 mu m. It consumes 163.9 mu W at 270 MHz with a 1.0 V power supply. The EMI reduction of the proposed ADSSCG is 13.99 dB with a 0.5% spreading ratio at 270 MHz, and 20.23 dB EMI reduction is achieved with a 1.5% spreading ratio at 162 MHz. Moreover, the proposed ADSSCG is designed with standard cells, and thus it can be ported to different process in a short time.

• 出版日期2013