A 0.89-mW 1-MHz 62-dB SNDR Continuous-Time DeltaSigma Modulator With an Asynchronous Sequential Quantizer and Digital Excess-Loop-Delay Compensation

作者：Weng Chan Hsiang^*; Lin Chen Chien; Chang Yu Cheng; Lin Tsung Hsien

来源：IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2011, 58(12): 867-871.

DOI：10.1109/TCSII.2011.2172709

• Asynchronous circuits
• delta-sigma modulator
• digitally assisted design
• excess loop delay (ELD)

A second-order continuous-time delta-sigma modulator incorporating a proposed 4-bit asynchronous sequential quantizer and a digital excess-loop-delay (ELD) compensation technique is presented. The sequential operation of the proposed quantizer facilitates low power consumption while the hardware-efficient digital compensation technique allows the modulator to accommodate ELD. With a 1-MHz bandwidth and a 60-MHz sampling rate, the measured peak signal-to-noise-and-distortion ratio and dynamic range are 62 and 67 dB, respectively. Fabricated in a 90-nm CMOS, this chip consumes only 0.89 mW from a 1.2-V supply.

• 出版日期2011-12
• 单位中国科学院电工研究所