A 1.2-GS/s 8-bit Two-Step SAR ADC in 65-nm CMOS With Passive Residue Transfer

作者：Huang Hai^*; Du Ling; Chiu Yun

来源：IEEE Journal of Solid-State Circuits, 2017, 52(6): 1551-1562.

DOI：10.1109/JSSC.2017.2682839

• 2b-1b/cycle conversion scheme
• analog-to-digital conversion
• high-speed successive-approximation-register (SAR) architecture
• passive residue transfer
• two-step SAR

A high-speed 2b-1b/cycle two-step successive-approximation- register analog-to-digital converter (ADC) exploiting the passive residue transfer technique is reported. The removal of the residue amplifier results in savings in the time and power consumed by the residue transfer process. The kT/C noise and potential bandwidth mismatch associated with the passive residue transfer are analyzed and also verified by circuit simulations. The use of the 2b-1b/cycle hybrid conversion scheme with an appropriate resolution partition further enhances the conversion speed. Fabricated in a 65-nm CMOS process, the prototype ADC measured a signal-to-noise plus distortion ratio of 43.7 dB and a spurious-free dynamic range of 58.1 dB for a near-Nyquist input. The total power consumption of the ADC is 5 mW and the achieved figure of merit is 35 fJ/conversion-step, all measured at a sample rate of 1.2 GS/s.

• 出版日期2017-6