An 8 bit 0.3-0.8 V 0.2-40 MS/s 2-bit/Step SAR ADC With Successively Activated Threshold Configuring Comparators in 40 nm CMOS

作者：Yoshioka Kentaro^*; Shikata Akira; Sekimoto Ryota; Kuroda Tadahiro; Ishikuro Hiroki

来源：IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2015, 23(2): 356-368.

DOI：10.1109/TVLSI.2014.2304733

• 2-bit/step
• extremely low voltage
• low power
• SAR ADC
• threshold configuring comparator

A 0.3-0.8 V low-power 2-bit/step asynchronous successive approximation register analog-to-digital converter (ADC) is presented. A low-power 2-bit/step operation technique is proposed which uses dynamic threshold configuring comparator instead of multiple digital-to-analog converters (DACs). Power and area overhead is minimized by successively activated comparators. The comparator threshold is configured by simple V-cm biased current source, which keep the ADC free from power supply variations over 10%. Simple digital calibration is enabled by generating the reference internally. The prototype ADC fabricated in a 40 nm CMOS achieved a 44.3 dB signal-to-noise-plus-distortion ratio (SNDR) with 6.14 MS/s at a single supply voltage of 0.5 V. The ADC achieved a peak FoM of 4.8 fJ/conv-step at 0.4 V and operates down to 0.3 V.

• 出版日期2015-2