Fabrication of poly-Si TFT with silicided Schottky barrier source/drain, high-kappa gate dielectric and metal gate

作者：Zhu SY; Singh J; Zhu CX; Du A; Li MF^*

来源：Solid-State Electronics, 2006, 50(2): 232-236.

DOI：10.1016/j.sse.2005.11.001

• TFT
• Schottky barrier source/drain
• silicide
• low temperature process

In this paper, a polycrystalline Si thin film transistor (TFT) with self-aligned silicide Schottky barrier source/drain (SSD), high-kappa gate dielectric and metal gate electrode is demonstrated using a simplified low temperature process. After crystallization of alpha-Si, the thermal budget for device fabrication is reduced to similar to 420 degrees C due to elimination of the implant doping and subsequent activation annealing procedures. P-channel SSD-TFT with PtSi S/D shows an acceptable electrical performance with I-on of 1.5 mu A/mu m for the L-g = 2.5 mu m device at V-gs = V-ds = -5 V and I-on/I-off ratio of similar to 10(4). However, I-on of the n-channel SSD-TFT with DySi2-x S/D is about two orders of magnitude smaller due to the relatively high Schottky barrier height and poor silicide quality of the DYSi2-x/poly-Si contact.

• 出版日期2006-2
• 单位复旦大学