Design of an 8 bit differential paired eFuse OTP memory IP reducing sensing resistance

作者：Jang Ji hye; Jin Li yan; Jeon Hwang Gon; Kim Kwang Il; Ha Pan Bong; Kim Young Hee^*

来源：Journal of Central South University, 2012, 19(1): 168-173.

DOI：10.1007/s11771-012-0987-4

• eFuse
• differential paired efuse cell
• one time programmable memory
• sensing resistance
• D flip-flop based sense amplifier

For the conventional single-ended eFuse cell, sensing failures can occur due to a variation of a post-program eFuse resistance during the data retention time and a relatively high program resistance of several kilo ohms. A differential paired eFuse cell is designed which is about half the size smaller in sensing resistance of a programmed eFuse link than the conventional single-ended eFuse cell. Also, a sensing circuit of sense amplifier is proposed, based on D flip-flop structure to implement a simple sensing circuit. Furthermore, a sensing margin test circuit is proposed with variable pull-up loads out of consideration for resistance variation of a programmed eFuse. When an 8 bit eFuse OTP IP is designed with 0.18 mu m standard CMOS logic of TSMC, the layout dimensions are 229.04 mu m x 100.15 mu m. All the chips function successfully when 20 test chips are tested with a program voltage of 4.2 V.

• 出版日期2012-1