摘要
Hash functions are among the crucial modules of modern hardware cryptographic systems. These systems frequently operate in harsh and noisy environments where permanent and/or transient faults are often causing erroneous authentication results and collapsing of the whole authentication procedure. Hence, their on-time detection is an urgent feature. In this paper, a systematic development flow towards totally self-checking (TSC) architectures of the most widely-used cryptographic hash families, SHA-1 and SHA-2, is proposed. Novel methods and techniques are introduced to determine the appropriate concurrent error detection scheme at high level avoiding gate-level implementations and comparisons. The resulted TSC architectures achieve 100% fault detection of odd erroneous bits, while, depending on the designer%26apos;s choice, even number of erroneous bits can also be detected. Two representative functions of the above families, namely the SHA-1 and SHA-256, are used as case studies. For each of them, two TSC architectures (one un-optimized and one optimized for throughput) were developed via the proposed flow and implemented in TSMC 0.18 mu m CMOS technology. The produced architectures are more efficient in terms of throughput/area than the corresponding duplicated-with-checking ones by 19.5% and 23.8% regarding the un-optimized TSC SHA-1 and SHA-256 and by 20.2% and 24.6% regarding the optimized ones.
- 出版日期2013-7