An 8 Bit 4 GS/s 120 mW CMOS ADC

作者：Wei, Hegong^*; Zhang, Peng; Sahoo, Bibhu Datta; Razavi, Behzad

来源：IEEE Journal of Solid-State Circuits, 2014, 49(8): 1751-1761.

DOI：10.1109/JSSC.2014.2313571

• Analog-to-digital conversion
• interleaving
• pipelined analog-to-digital converter (ADC)
• time error detection and correction
• timing calibration
• variable delay lines

A time-interleaved ADC employs four pipelined time-interleaved channels along with a new timing mismatch detection algorithm and a high-resolution variable delay line. The digital background calibration technique suppresses the interchannel timing mismatches, achieving an SNDR of 44.4 dB and a figure of merit of 219 fJ/conversion-step in 65 nm CMOS technology.

• 出版日期2014-8
• 单位清华大学