Algorithm and hardware design of a 2D sorter-based K-best MIMO decoder

作者：Thi Hong Tran^*; Nagao Yuhei; Ochi Hiroshi

来源：EURASIP Journal on Wireless Communications and Networking, 2014, 2014(1): 93.

DOI：10.1186/1687-1499-2014-93

• Maximum likelihood detection (MLD)
• K-best
• MIMO decoder
• IEEE 802.11n/ac
• 256-QAM

In the field of multiple input multiple output (MIMO) decoder, K-best has been well investigated because it guarantees an SNR-independent fixed-throughput with a performance close to the optimal maximum likelihood detection (MLD). However, the complexity of its expansion and sorting tasks is significantly affected by the constellation size W. In this paper, we propose an algorithm and hardware design of a 2D sorter-based K-best MIMO decoder whose complexity is negligibly affected by W. The main novelties of the algorithm are the following: (1) Direct expansion and parent node grouping ideas are proposed for reducing the expansion task's complexity. (2) Two-dimensional (2D) sorter is proposed for simplifying the sorting task. The hardware design of the decoder supports up to 256-QAM modulation, which aims to apply into 4 x 4 MIMO 802.11n and 11ac systems. The paper shows that the proposed decoder outperforms the Bell Labs layered space-time (BLAST) minimum mean square error (MMSE) and lattice-reduction aided (LRA) MMSE, and is close to the full K-best in terms of bit error rate (BER) performance. The hardware design of the decoder is synthesized in application specific integrated circuit (ASIC) and compared with the previous works. As a result, it achieves the highest throughput (up to 2.7 Gbps), consumes the least power (56 mW), obtains the best hardware efficiency (15.2 Mbps/Kgate), and has the shortest latency (0.07 A mu s).

• 出版日期2014-6-12