Digit-serial complex-number multipliers on FPGAs

作者：Sansaloni Trinidad; Valls Javier; Parhi Keshab K.^*

来源：Journal of Vlsi Signal Processing Systems for Signal, Image, and Video Technology, 2003, 33(1-2): 105-115.

DOI：10.1023/A:1021197903170

• Booth recoding

This paper presents an optimized implementation on FPGA of digit-serial Complex-Number Multipliers (CMs) using Booth recoding techniques and tree adders based on Carry Save (CS) and Ripple Carry Adders (RCA). This kind of Complex-Number multipliers can be pipelined at the same level independent of the digit-size. Variable and fixed coefficient CMs have been considered. In the first case an efficient mapping of the modified Booth recoding and the partial product generation is presented which results in a logic depth reduction. The combination of 5:3 and 4:3 converters in the CS structure and the utilization of RCA trees lead to a minimum area requirement. In the case of fixed coefficient CMs, partial products generator is based on look-up tables and multi-bit Booth recoding is used to reduce the area and increase the performance of the circuit. The study reveals that efficient mapping of the 5-bit Booth recoding to generate the partial products is the optimum multibit recoding when Xilinx FPGA devices are used.

• 出版日期2003