科研之友
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摘要
We propose a 8 bit two stage time-to-digital converter (TDC) using a time difference amplifier. The time resolution is 1.89 ps, and DNL of 0.9 and INL of 1.0 are achieved in simulation assuming the standard 0.18 um CMOS. To amplify the time residue of the first stage, the 16x cascaded time difference amplifier (TDA) using differential logic delay cells is employed. Time resolution of the proposed TDC becomes finer by employing the 16x cascaded TDA and the linearity is improved by using only one TDA in the two stage TDC instead of using a lot of TDAs.
- 出版日期2010-7-10
