A 20 GS/s 1.2 V 0.13 mu m CMOS Switched Cascode Track-and-Hold Amplifier

作者：Orser Heather^*; Gopinath Anand

来源：IEEE Transactions on Circuits and Systems II-Express Briefs, 2010, 57(7): 512-516.

DOI：10.1109/TCSII.2010.2048484

• High-speed integrated circuits
• sample-and-hold amplifiers (SHAs)
• sampled data circuits
• track-and-hold amplifiers (THAs)

A low voltage, low power, high sampling rate track-and-hold amplifier (THA) architecture is proposed. The THA samples at 20 GS/s and combines a distributed amplifier and a switched cascode stage. Power consumption for the circuit is 71 mW and it occupies 0.09 mm(2) in 0.13 mu m CMOS. The THA delivers up to 34 dB spur-free dynamic range (SFDR) and -32 dB total harmonic distortion (THD) at a supply voltage of 1.2 V. Input return loss remains below -10 dB over all frequencies of interest, while output return loss remains below -15 dB.

• 出版日期2010-7