An effective BIST scheme for SRAM full speed test

作者：Zhang, Lijun^*; Yu, Yue; Zheng, Jianbin; Song, Xiaoyu

来源：International Journal of Electronics, 2011, 98(9): 1281-1290.

DOI：10.1080/00207217.2011.593136

• SRAM
• BIST
• delay chain
• four phase clock
• full speed test

This article presents a novel built-in self-test (BIST) scheme at full speed test where access time test is performed. Based on normal BIST circuits, we harness an all digital phase locked loop to generate a high-frequency clock for static random access memory (SRAM) performance test at full speed. A delay chain is incorporated to achieve the four-phase clock. As inputs to SRAM, clock, address, data are generated in terms of the four-phase clock. Key performance parameters, such as access time, address setup and hold times, are measured. The test chip has been fabricated by United Microelectronics Corporation 55 nm CMOS logic standard process. According to test results, the maximum test frequency is about 1.3 GHz, and the test precision is about 35 ps at the typical process corner with supply voltage 1.0V and temperature 25 degrees C.

• 出版日期2011
• 单位苏州大学