摘要

A high-gain and low-noise micromachined CMOS distributed amplifier (DA) using cascaded gain cell, which constitutes an inductively parallel-peaking cascode-stage with a low-Q RLC load and an inductively series-peaking common-source stage, is demonstrated.Flat and high S21 and flat and low noise figure (NF) are achieved simultaneously by adopting a slightly under-damped Q-factor for the second-order transconductance frequency response of the proposed cascaded gain cell. The two-stage DA consumes 37.8 mW and achieves flat and high S21 of 20.47 +/- 0.72 dB with an average NF of only 3.3 dB over the 3 similar to 10 GHz band of interest, one of the best reported NF performances for a CMOS UWB DA or LNA in the literature. In addition, the result shows that a 0.84-dB increase in average S21 (from 20.47 to 21.31 dB) and a 0.2-dB decrease (from 3.3 to 3.1 dB) in average NF are achieved mainly due to the improvement of the quality factor of the inductors in the DA. This means that this DA architecture in conjunction with the backside ICP dry-etching technique is very promising for high-performance 3 similar to 10 GHz UWB communication systems.

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