Multichip Self-Assembly Technology for Advanced Die-to-Wafer 3-D Integration to Precisely Align Known Good Dies in Batch Processing

作者：Fukushima Takafumi^*; Iwata Eiji; Ohara Yuki; Murugesan Mariappan; Bea Jichoel; Lee Kangwook; Tanaka Tetsu; Koyanagi Mitsumasa

来源：IEEE Transactions on Components Packaging and Manufacturing Technology, 2011, 1(12): 1873-1884.

DOI：10.1109/TCPMT.2011.2160266

• 3-D integration
• alignment and bonding
• die-to-wafer stacking
• liquid surface tension
• self-assembly

An advanced die-to-wafer 3-D integration using a surface-tension-driven multichip self-assembly technology was proposed to 3-D stack a large number of known good dies (KGDs) in batch processing. The parallel self-assembly with a unique multichip pick-up tool was newly applied to die-to-wafer 3-D integration to overcome throughput and yield problems in conventional 3-D integration approaches. In addition, novel batch transfer of chips self-assembled on a carrier wafer to the corresponding target wafer was demonstrated. By using the multichip self-assembly, many KGDs can be precisely aligned and temporarily placed on a carrier wafer all at once, and then, the self-assembled KGDs can be simultaneously transferred to another target wafer in a face-to-face bonding manner at the wafer level. Average alignment accuracy was found to be approximately 400 nm when a hundred 3-mm-square chips were self-assembled on carrier wafers with small droplets of an aqueous solution. The alignment accuracy was experimentally proven to be fairly dependent on liquid surface tension as a self-assembly parameter. The liquid wettability contrast between the chip assembly areas and the surrounding areas formed on carrier wafers was another key parameter for alignment accuracy. The former and the latter areas were rendered high hydrophilic and hydrophobic. These areas, respectively, showed water contact angles less than 5 degrees and 115 degrees. Therefore, various sizes of chips (3 x 3 mm, 5 x 5 mm, 4 x 9 mm, and 10 x 10 mm) were self-assembled on a carrier wafer with high alignment accuracy, and further, the self-assembled chips were successfully transferred to the other faced target wafer in a batch.

• 出版日期2011-12