A 0.8-mW 5-bit 250-MS/s Time-Interleaved Asynchronous Digital Slope ADC

作者：Harpe Pieter J A^*; Zhou Cui; Philips Kathleen; de Groot Harmke

来源：IEEE Journal of Solid-State Circuits, 2011, 46(11): 2450-2457.

DOI：10.1109/JSSC.2011.2164031

• ADC
• analog-to-digital conversion
• asynchronous
• CMOS
• slope ADC
• ramp ADC

Slope and digital-ramp converters are normally limited to very low sampling rates, since they require a digital counter at a highly oversampled clock rate. In this work, an asynchronous digital slope architecture is introduced that only requires a nonoversampled clock, thus enabling a much higher speed of operation. At the same time, the low complexity and the inherent accuracy of the slope-architecture enable very good power-efficiency without using complex calibration techniques. A two-channel time-interleaved 5-bit asynchronous digital slope ADC was implemented in a 90-nm CMOS technology and occupies 160 mu m x 300 mu m. The measured prototype achieves an ENOB of 4.6 bit, while operating at 250 MS/s and consuming 0.8 mW from a 1-V supply.

• 出版日期2011-11