A 65 nm CMOS analog processor with zero dead time for future pixel detectors

作者：Gaioni L^*; Braga D; Christian D C; Deptuch G; Fahim F; Nodari B; Ratti L; Re V; Zimmerman T

来源：Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment , 2017, 845: 595-598.

DOI：10.1016/j.nima.2016.04.053

• Pixel detectors
• Analog front-end
• CMOS
• Zero dead time processor
• High-Luminosity LHC

Next generation pixel chips at the High-Luminosity (HL) LHC will be exposed to extremely high levels of radiation and particle rates. In the so-called Phase II upgrade, ATLAS and CMS will need a completely new tracker detector, complying with the very demanding operating conditions and the delivered luminosity (up to 5 x 10(34) cm(-2) s(-1) in the next decade). This work is concerned with the design of a synchronous analog processor with zero dead time developed in a 65 nm CMOS technology, conceived for pixel detectors at the HL-LHC experiment upgrades. It includes a low noise, fast charge sensitive amplifier featuring a detector leakage compensation circuit, and a compact, single ended comparator that guarantees very good performance in terms of channel-to-channel dispersion of threshold without needing any pixel-level trimming. A flash ADC is exploited for digital conversion immediately after the charge amplifier. A thorough discussion on the design of the charge amplifier and the comparator is provided along with an exhaustive set of simulation results.

• 出版日期2017-2-11