A Complete Charge Recycling TCAM with Checkerboard Array Arrangement for Low Power Applications

作者：Dosaka Katsumi^*; Ogawa Daisuke; Kusumoto Takahito; Miyama Masayuki; Matsuda Yoshio

来源：IEICE - Transactions on Electronics, 2010, E93C(5): 685-695.

DOI：10.1587/transele.E93.C.685

• TCAM
• charge recycling
• low power
• low noise
• low operating current

Architecture of a low power Ternary Content Addressable Memory (TCAM) is proposed. The TCAM is a powerful engine for search and sort processing, but it has two serious problems, large power consumption and large power line noise. To solve these problems, we have developed a charge recycling scheme for match lines and search lines. A combination of the newly introduced PMOS CAM cell together with the conventional NMOS CAM cell realizes match line charge recycling. A checkerboard arrangement of the NMOS and the PMOS cell array enables search line charge recycling. By using these technologies, the power consumption of the TCAM can be reduced to 50% of conventional designs, and as a result, the power line noise is also reduced. An experimental chip has been fabricated in 180-nm 6-metal process. The power consumption of this chip is 6.3 fJ/bit/search, which is half of the conventional scheme.

• 出版日期2010-5