A Built-In Self-Repair Scheme for 3-D RAMs With Interdie Redundancy

作者：Chou Che Wei^*; Huang Yu Jen; Li Jin Fu

来源：IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2013, 32(4): 572-583.

DOI：10.1109/TCAD.2012.2222882

• 3-D integrated circuit (IC)
• 3-D random access memory (RAM)
• memory repair
• memory testing
• through-silicon-via (TSV)
• yield improvement

3-D integration using through silicon via is an emerging technology for integrated circuit designs. Random access memory (RAM) is one good candidate for the application of 3-D integration technology. However, yield will be a key challenge for the volume production of 3-D RAMs. In this paper, we present yield-enhancement techniques for 3-D RAMs. An interdie redundancy scheme is proposed to improve the yield of 3-D RAMs. Three stacking flows with respect to different bonding technologies for 3-D RAMs with interdie redundancy are proposed as well. Finally, a built-in self-repair (BISR) scheme is proposed to perform the repair of 3-D RAMs with interdie redundancies. The BISR circuits in two stacked dies can work together to allocate interdie redundancies. Simulation results show that the proposed yield-enhancement techniques can effectively improve the yield of 3-D RAMs.

• 出版日期2013-4
• 单位中央民族大学