A multiwindow partial buffering scheme for FPGA-based 2-D convolvers

作者：Zhang Hui^*; Xia Mingxin; Hu Guangshu

来源：IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2007, 54(2): 200-204.

DOI：10.1109/TCSII.2006.886898

• field-programmable gate arrays (FPGAs)
• full buffering (FB)
• multiwindow (MW)
• partial buffering (PB)
• two-dimensional (2-D) convolution

Two-dimensional (2-D) convolution is widely used in image and video processing. Although the operation is simple, 2-D convolution is however both computationally expensive and memory-intensive. Field-programmable-gate-array (FPGA)-based parallel processing architectures were proposed to accelerate calculations for 2-D convolution. And data buffers implemented with FPGA on-chip resources were used to avoid direct access to external memories. Full buffering and partial buffering (PB) schemes were adopted in previous works. The former would consume a large amount of FPGA resources, while the latter would cause a sharp increase in external memory bus bandwidth. In this brief, we present a multiwindow PB scheme for FPGA-based 2-D convolvers. Compared with the aforementioned methods, the new buffering strategy exhibits a good balance between on-chip resource utilization and external memory bus bandwidth, and therefore is suitable for low-cost FPGA implementation.

• 出版日期2007-2
• 单位清华大学