A Runtime Optimization Approach for FPGA Routing

作者：Wang, Dekui; Duan, Zhenhua^*; Tian, Cong^*; Huang, Bohu; Zhang, Nan

来源：IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2018, 37(8): 1706-1710.

DOI：10.1109/TCAD.2017.2768416

• Field-programmable gate array (FPGA) routing
• PathFinder
• rerouting strategy
• routing algorithm
• maze router

In this paper, we present a new field-programmable gate array (FPGA) routing approach on the basis of the PathFinder routing algorithm. During each routing iteration, our approach applies a novel timing-based rerouting strategy to only reroute the illegal paths. At a lower level, each maze expansion is started from the relatively dose part of current routing tree to search for the target sink on the routing resource graph. Experimental results demonstrate that on average the proposed approach reduces the routing runtime by 68.5% compared with the timing-driven router in versatile place and route FPGA placement and routing framework, with reduction of 2.5% and 1.4% in critical path delay and wirelength, respectively.

• 出版日期2018-8
• 单位西安电子科技大学