A 1-pJ/bit, 10-Gb/s/ch Forwarded-Clock Transmitter Using a Resistive Feedback Inverter-Based Driver in 65-nm CMOS

作者：Bae Woorham; Jeong Gyu Seob; Jeong Deog Kyoon^*

来源：IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2016, 63(12): 1106-1110.

DOI：10.1109/TCSII.2016.2618896

• CMOS
• forwarded clock (FC)
• phase-locked loop (PLL)
• transmitter
• wireline

An energy-efficient forwarded-clock transmitter that offers a scalable pre-emphasis equalization and output voltage swing is presented. A resistive-feedback inverter-based driver is used to overcome the drawbacks of the conventional drivers. Moreover, half-rate clocking structure is employed in order to minimize power consumption in 65-nm CMOS technology. The proposed transmitter consists of two data lanes, a shared clock lane, and a global impedance regulator. The prototype chip is fabricated in 65-nm CMOS technology and occupies an active area of 0.15 mm(2). The proposed transmitter achieves 100-250 mV single-ended swing and exhibits the energy efficiency of 1 pJ/bit at the per-pin data rate of 10 Gb/s.

• 出版日期2016-12