Limits of predictive current-ripple suppression in switching power-supply ICs

作者：Milner L A^*; Rincon Mora G A

来源：IET Power Electronics, 2010, 3(1): 43-53.

DOI：10.1049/iet-pel.2008.0231

Large inductance requirements (for accuracy) in switching power supplies for portable applications impede system-on-chip (SoC) integration and therefore form-factor reduction because on-chip inductances are invariably low and off-chip inductors intolerably obtrusive. Cancelling the current ripple of innately small on-chip inductors, however, keeps the effective output current ripple and its resulting output voltage variation (i.e. accuracy) within acceptable window limits (e.g. 50-200 mA and 20-50 mV), effectively multiplying the on-chip inductance and circumventing the need for bulky off-chip inductors. To this end, while gyrators and other voltage-mode inductor multiplier circuitry simulate relatively high inductances, they cannot supply the 250-750 mW loads typically attached to battery-powered switching regulators, which the predictive current-mode multipliers discussed in this paper can. The basic objective is to cancel the ac inductor current ripple with an inverting ac replica and allow the on-chip inductor to source the full dc load. Ac mismatches in the form of amplitude, delay and non-linearity, however, limit the extent to which the original ac ripple is cancelled, constraining the inductor multiplication factor to finite values. The foregoing paper describes, illustrates and derives the effects of these mismatches on the multiplication factor and shows how realistic non-idealities (e.g. up to 10% gain error and less than 10 ns of delay) can yield inductance multiplication factors of 125 H/H at 100 kHz and 11.5 H/H at 10 MHz in a practical switching dc dc power-supply integrated circuit (IC).

• 出版日期2010-1