A Fast-Locking All-Digital Deskew Buffer With Duty-Cycle Correction

作者：Chen You Gang^*; Tsao Hen Wai; Hwang Chorng Sii

来源：IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2013, 21(2): 270-280.

DOI：10.1109/TVLSI.2011.2182216

• Delay-locked loop (DLL)
• duty-cycle correction (DCC)
• edge combiner
• time-to-digital converter (TDC)

In this paper, a fast-locking all-digital deskew buffer with duty cycle correction is proposed and implemented. A cyclic time-to-digital converter is introduced to decrease the locking time in conventional register-controlled delay-locked loop to only two input clock cycles in coarse tuning. With the aid of the three half delay lines technique, the mismatch between half delay lines causing the duty cycle distortion can be alleviated by interpolation. A balanced edge combiner to achieve a precise 50% output clock is also presented. A test chip is fabricated in 0.18-m technology to demonstrate the feasibility of the proposed architecture. The circuit can accept the input clock rates from 250 to 625 MHz with the duty cycle variation within 30% and 70% to generate 50% output clocks. It preserves the capability of closed-loop control with a small area and power consumption.

• 出版日期2013-2
• 单位中国科学院电工研究所