A 2.4GHz CMOS Doherty power amplifier with capacitance compensation technique

作者：Xiong, Fa Ke; Mo, Ting Ting

来源：13th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2016, China,Zhejiang,Hangzhou, 2016-10-25 to 2016-10-28.

DOI：10.1109/ICSICT.2016.7998938

• Capacitance compensation
• Cascode transistors
• Doherty power amplifier
• IMD3
• Input capacitance
• Power-added efficiency
• Quarter wave transmission lines
• Third order intermodulation distortion

A 2.4GHz Doherty power amplifier (DPA) using capacitance compensation is proposed in 0.18um TSMC process. Doherty configuration with self-biased cascode transistors is adopted to achieve high output power and efficiency in power back-off region. The lumped element π-network is employed to replace the quarter wave transmission lines and facilitates the integration. Placing the PMOS device in parallel with the NMOS device as a amplifier to cancel the variation of the input capacitance of the NMOS device and then improves the linearity. This prototype has a power-added efficiency (PAE) of 32.5% at a P1dB of 22.9dBm from 2.5V supply voltage. The PAE at 5dB back-off is still as high as 17.8%. The third order intermodulation distortion (IMD3) in a range of 5-10 dB improvement compared with the compensation and without compensation, reveals the linearity enhancement of the proposed PA.

• 出版日期2016
• 单位上海交通大学