A 10-bit dual-plate sampling DAC with capacitor reuse on-chip reference voltage generator

作者：Gaddam Ravi Shankar; Lee Kye Shin^*; Kwon Chun Ki

来源：Microelectronics Journal, 2013, 44(6): 511-518.

DOI：10.1016/j.mejo.2013.03.004

• Capacitive DAC
• Capacitor reuse
• Dual-plate sampling
• Offset cancellation
• Reference voltage generator

In this work, a 10-bit dual-plate sampling capacitive DAC with a capacitor reuse on-chip reference voltage generator is proposed. Instead of using the conventional two element switched-capacitor circuit that consists of the charge sampling and summing capacitors, the proposed dual-plate sampling scheme performs the identical operation using a single capacitor. As a result, the capacitor area can be significantly reduced compared to conventional capacitive DACs. Furthermore, the capacitor reuse reference voltage generator does not add much area and power overhead, and the reference amplifier offset cancellation alleviates the reference matching requirements. The proposed DAC is implemented using the CMOS 035 gm technology with core size of 0.11 mm(2) and power consumption of 0.8 mW for conversion rate of 1.75 MS/s. The maximum INL and DNL showed 0.89 LSB and 0.47 LSB, respectively.

• 出版日期2013-6