科研之友
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摘要
A digital carrier synchronization module with high working frequency is indispensable for high-speed digital coherent optical receivers to recover the transmitted symbols. We proposed a method to increase the working frequency of the digital carrier synchronization (DCS) module based on the commonly used M'th power algorithms. Parallel architecture can increase the throughput of digital signal processing (DSP) modules for a given working frequency. pipelined architecture (PA) leads to a reduction in the critical path, and thus it can be exploited to increase the throughput of DSP modules by increasing the working frequency. It is demonstrated that in PA the working frequency is not limited by the computation time of the M'th power subfunction with the highest complexity because it is feedforward and thus pipelining registers can be introduced to reduce the critical path inside it. Instead, the phase unwrapping subPUS) becomes the bottleneck of the working frequency because it requires the immediately preceding result and cannot be implemented in PA, which results in the longest critical path among the DCS module. To solve this problem, we propose a feedforward look-uptable-based PUS design that can greatly reduce the critical path and increase the working frequency. Experimental DCS implementation in a Xilinx Virtex7 field programmable gate array shows that with this method the working frequency of the DCS module for quadrature phase-shift keying (QPSK) signals can be increased by 63.8%. Furthermore, using experimental and simulation data, it is demonstrated that the performance of the DCS module with increased working frequency is close to that of the off-line DCS algorithms for QPSK signals.
- 出版日期2017-8
- 单位华中科技大学
