A 4th Order 3.6 GS/s RF Sigma Delta ADC With a FoM of 1 pJ/bit

作者：Ashry Ahmed^*; Aboushady Hassan

来源：IEEE Transactions on Circuits and Systems I-Regular Papers, 2013, 60(10): 2606-2617.

DOI：10.1109/TCSI.2013.2248832

• ADC
• analog digital conversion
• CMOS analog integrated circuits
• continuous-time Sigma Delta
• RF sampling
• SDR
• sigma delta modulation
• software-defined radio

A 4th order RF LC-based Sigma Delta ADC clocked at 3.6 GHz and centered at 900 MHz is presented. A simple design methodology is used to derive a robust architecture with a minimum number of feedback coefficients. The simplicity of the ADC architecture results in a significant performance enhancement and power consumption reduction. An efficient algorithm for the tuning and calibration of the Sigma Delta LC-based loop filter is also presented. The ADC, suitable for cognitive Software Defined Radio applications, is implemented in a standard 130 nm CMOS technology. It achieves a 52 dB SFDR and a 50 dB SNR in a 28 MHz BW and consumes only 15 mW from a 1.2 V supply. The Figure of Merit of the ADC is 1.0 pJ/bit, which is to date the best reported FoM for an RF ADC. The effect of the clock jitter on the ADC performance is also measured and presented.

• 出版日期2013-10