A 6-bit 4 MS/s, V-CM-based sub-radix-2 SAR ADC with inverter type comparator

作者：Rikan Behnam Samadpoor; Lee DongSoo; Lee Kang Yoon^*

来源：MICROELECTRONICS JOURNAL, 2017, 62: 120-125.

DOI：10.1016/j.mejo.2017.02.009

• SAR ADC
• CMOS
• Comparator
• Non-binary DAC

This paper presents a 6-bit sub-radix-2 redundant V-CM-based SAR ADC for BLE transceiver applications. The basic trend for BLE applications is to reduce area and power consumption. In order to reduce switching power consumption, V-CM-based straightforward CDAC is applied. Custom-designed 600 aF unit capacitor minimizes the area and analog power consumption of the ADC. Sub-radix-2 redundant architecture, as well as digital calibration, is applied for CDAC which guarantees digitally correctable static nonlinearities of the converter and dynamic errors in the conversion process occurs due to small capacitor sizes. The structure applies an inverter type comparator to reduce the area. The prototype ADC is fabricated and measured in a 55 nm CMOS process and achieves 5.31-5.89 ENOB at 4 MS/s sampling frequency. SNDR and SFDR for Nyquist input frequency are 33.73 dB and 40.2 dB respectively. The current consumption is 3.7 mu A from a 1.0 V supply, which corresponds to 23 fJ/step FOM. The active area of the core ADC is 100 mu m x 45 mu m.

• 出版日期2017-4