A BJT-Based Temperature-to-Digital Converter With +/- 60 mK (3 sigma) Inaccuracy From-55 degrees C to+125 degrees C in 0.16-mu m CMOS

作者：Yousefzadeh Bahman^*; Shalmany Saleh Heidary; Makinwa Kofi A A

来源：IEEE Journal of Solid-State Circuits, 2017, 52(4): 1044-1052.

DOI：10.1109/JSSC.2016.2638464

• Batch calibration
• low-cost calibration
• proportional to absolute temperature (PTAT) trim
• substrate PNP
• temperature sensor
• temperature-to-digital converter (TDC)

This paper presents a precision CMOS temperature-to-digital converter (TDC), which senses the temperature-dependent base-emitter voltage of substrate PNPs. Measurements on 20 samples from one batch show that it achieves an inaccuracy of +/- 60 mK (3 sigma) from- 55. degrees C to + 125. degrees C, after a single room-temperature trim. This state-of-the-art result is mainly due to the extensive use of dynamic error cancellation techniques to generate the PNP's collector currents, thus minimizing the spread in their base-emitter voltages, together with a digital PTAT trim to correct for the spread in the PNP's saturation currents. The effect of process variation on the TDC's inaccuracy was investigated by measuring 80 samples from three different batches. Using the same calibration parameters, they exhibit a maximum untrimmed inaccuracy of +/- 2. degrees C (3 sigma) from - 55. degrees C to + 125. degrees C. This drops to +/- 100 mK (3 sigma) after a single point trim. The proposed TDC thus reduces calibration costs by obviating the need for batch-specific calibration parameters, which would otherwise require the multipoint calibration of several samples. The effect of the PNP's current gain beta was also investigated with the help of a novel beta-detection circuit. Implemented in 0.16-mu m CMOS, the TDC occupies 0.16 mm(2) and draws 4.6 mu A from 1.5 to 2 V supply voltages. It achieves a resolution Figure of Merit of 7.8 pJ degrees C-2, and a state-of-the-art supply sensitivity of 0.01 degrees C/V.

• 出版日期2017-4