A 1.25 GHz Low Power Multi-phase PLL Using Phase Interpolation between Two Complementary Clocks

作者：Jin Xuefan^*; Bae Jun Han; Chun Jung Hoon; Kim Jintae; Kwon Kee Won

来源：Journal of Semiconductor Technology and Science, 2015, 15(6): 594-600.

DOI：10.5573/JSTS.2015.15.6.594

• Phase interpolation
• PLL
• PFD controller
• phase-rotating PLL

A 1.25 GHz multi-phase phase-rotating PLL is proposed for oversampling CDR applications and implemented with a low power and small area. Eight equidistant clock phases are simultaneously adjusted by the phase interpolator inside the PLL. The phase interpolator uses only two complementary clocks from a VCO, but it can cover the whole range of phase from 0 degrees to 360 degrees with the help of a PFD timing controller. The output clock phases are digitally adjusted with the resolution of 25 ps and both INL and DNL are less than 0.44 LSB. The proposed PLL was implemented using a 110 nm CMOS technology. It consumes 3.36 mW from 1.2 V supply and occupies 0.047 mm(2). The jitter(rms) and jitterpk-pk of the output clock are 1.91 ps and 18 ps, respectively.

• 出版日期2015-12