A 28 nm FDSOI Integrated Reconfigurable Switched-Capacitor Based Step-Up DC-DC Converter With 88% Peak Efficiency

作者：Biswas Avishek^*; Sinangil Yildiz; Chandrakasan Anantha P

来源：IEEE Journal of Solid-State Circuits, 2015, 50(7): 1540-1549.

DOI：10.1109/JSSC.2015.2416315

• Body biasing
• bottom-plate parasitic capacitance
• FDSOI
• reconfigurable
• step-up DC-DC converter
• switched capacitor
• voltage overstress limitation

This paper presents a fully integrated, reconfigurable switched-capacitor based step-up DC-DC converter in a 28 nm FDSOI process. Three reconfigurable step-up conversion ratios (5/2, 2/1, 3/2) have been implemented which can provide a wide range of output voltage from 1.2 V to 2.4 V with a nominal input voltage of 1 V. We propose a topology for the 5/2 mode which improves the efficiency by reducing the bottom-plate parasitic loss compared to a conventional series-parallel topology, while delivering the same amount of output power. Further, the proposed topology benefits from using core 1 V devices for all charge-transfer switches without incurring any voltage overstress. The converter can deliver load current in the range of 10 mu A to 500 mu A, achieving a peak efficiency of 88%, using only on-chip MOS and MOM capacitors for a high density implementation.

• 出版日期2015-7