A Low Power Dual CDS for a Column-Parallel CMOS Image Sensor

作者：Cho Kyuik^*; Kim Daeyun; Song Minkyu

来源：Journal of Semiconductor Technology and Science, 2012, 12(4): 388-396.

DOI：10.5573/JSTS.2012.12.4.388

• CMOS image sensor
• correlated double sampling
• digital CDS
• dual CDS

In this paper, a 320 x 240 pixel, 80 frame/s CMOS image sensor with a low power dual correlated double sampling (CDS) scheme is presented. A novel 8-bit hold-and-go counter in each column is proposed to obtain 10-bit resolution. Furthermore, dual CDS and a configurable counter scheme are also discussed to realize efficient power reduction. With these techniques, the digital counter consumes at least 43% and at most 61% less power compared with the column-counters type, and the frame rate is approximately 40% faster than the double memory type due to a partial pipeline structure without additional memories. The prototype sensor was fabricated in a Samsung 0.13 mu m 1P4M CMOS process and used a 4T APS with a pixel pitch of 2.25 mu m. The measured column fixed pattern noise (FPN) is 0.10 LSB.

• 出版日期2012-12