An On-Chip Delay Measurement Technique Using Signature Registers for Small-Delay Defect Detection

作者：Katoh Kentaroh^*; Namba Kazuteru; Ito Hideo

来源：IEEE Transactions on Very Large Scale Integration Systems, 2012, 20(5): 804-817.

DOI：10.1109/TVLSI.2011.2125994

• Delay estimation
• design for testability (DFT)
• integrated circuit measurements
• semiconductor device reliability
• signature register

This paper presents a delay measurement technique using signature analysis, and a scan design for the proposed delay measurement technique to detect small-delay defects. The proposed measurement technique measures the delay of the explicitly sensitized paths with the resolution of the on-chip variable clock generator. The proposed scan design realizes complete on-chip delay measurement in short measurement time using the proposed delay measurement technique and extra latches for storing the test vectors. The evaluation with Rohm 0.18-mu m process shows that the measurement time is 67.8% reduced compared with that of the delay measurement with standard scan design on average. The area overhead is 23.4% larger than that of the delay measurement architecture using standard scan design, and the difference of the area overhead between enhanced scan design and the proposed method is 7.4% on average. The data volume is 2.2 times of that of test set for normal testing on average.

• 出版日期2012-5