A SAR-ADC using unit bridge capacitor and with calibration for the front-end electronics of PET imaging

作者：Liu, Wei; Wei, Tingcun^*; Li, Bo; Yang, Lifeng; Xue, Feifei; Hu, Yongcai

来源：Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment , 2016, 818: 9-13.

DOI：10.1016/j.nima.2016.02.048

• Front-end electronics
• CZT detector
• PET imaging
• SAR-ADC
• Spilt-capacitor DAC

This paper presents a 12-bit 1 MS/s successive approximation register-analog to digital converter (SAR-ADC) for the 32-channel front-end electronics of CZT-based PET imaging system. To reduce the capacitance mismatch, instead of the fractional capacitor, the unit capacitor is used as the bridge capacitor in the split-capacitor digital to analog converter (DAC) circuit. In addition, in order to eliminate the periodical DNL errors of -1 LSB which often exists in the SAR-ADC using the charge-redistributed DAC, a calibration algorithm is proposed and verified by the experiments. The proposed 12-bit 1 MS/s SAR-ADC is designed and implemented using a 0.35 mu m CMOS technology, it occupies only an active area of 986 x 956 mu m(2). The measurement results show that, at the power supply of 3.3/5.0 V and the sampling rate of 1 MS/s, the ADC with calibration has a signal-to-noise-and-distortion ratio (SINAD) of 67.98 dB, the power dissipation of 5 mW, and a figure of merit (FOM) of 2.44 pJ/conv.-step. This ADC is with the features of high accuracy, low power and small layout area, it is especially suitable to the one-chip integration of the front-end readout electronics.

• 出版日期2016-5-11
• 单位西北工业大学