A 0.0052 mm(2) COMPACT DIGITAL PLL IN 65 nm CMOS

作者:Luo Zhihong*; Au Yeung On; Lau Benjamin; Law Henry
来源:Journal of Circuits, Systems, and Computers, 2012, 21(8): 1240026.
DOI:10.1142/S0218126612400269

摘要

A novel structure of digital phase locked loop (PLL) is presented in this paper. It uses digitally controlled oscillator (DCO) to generate the clock. At the beginning of each reference clock cycle, the DCO is fully reset and restarts to oscillate to prevent the long term jitter accumulation and increase the loop stability. It uses three types of digital delay control methods, including delay cell number adjust, delay cell load adjust and in cycle load adjust to digitally control the DCO output clock frequency, in order to get wider frequency range and smaller jitter. This digital PLL uses NAND gate as the basic delay cell of ring oscillator, which can completely reset DCO in a very short time. It uses binary search to achieve fast lock and uses shift chain to get better input clock jitter tolerance. This digital PLL has been silicon validated in GLOBALFOUNDRIES 65 nm Generic process. Its chip area is only 0.0052 mm(2). In typical condition, DCO's frequency has a wide range between 550 MHz and 2.45 GHz. Its total power is around 1.4 mW when DCO's frequency is 1.8 GHz. This PLL can be locked very fast in 25 divided reference clock cycles, and its output clock jitter is around 18 ps.

  • 出版日期2012-12

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